The present invention relates to a circuit for magnetic memory, and more particularly, to embodiments of a sensing circuit for magnetic random access memory to emulate dynamic random access memory (DRAM).
Magnetic random access memory (MRAM) is a new class of non-volatile memory. Unlike volatile memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM) that loses the stored information when power is interrupted, non-volatile memory can retain the stored information even when powered off.
An MRAM device normally comprises an array of memory cells, each of which includes at least a magnetic memory element and an access transistor coupled in series between a bit line and a source line. Upon application of an appropriate current or voltage to the magnetic memory element in the programming step, the electrical resistance of the magnetic memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
A magnetic memory element normally includes a magnetic reference layer and a magnetic free layer with an electron tunnel junction layer interposed therebetween. The magnetic reference layer, the electron tunnel junction layer, and the magnetic free layer collectively form a magnetic tunneling junction (MTJ). Upon the application of an appropriate current or voltage to the MTJ, the magnetization direction of the magnetic free layer can be switched between two directions: parallel and anti-parallel with respect to the magnetization direction of the magnetic reference layer. The electron tunnel junction layer is normally made of an insulating material with a thickness ranging from a few to a few tens of angstroms. When the magnetization directions of the magnetic free and reference layers are substantially parallel or oriented in a same direction, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistance of the MTJ. Conversely, the electrical resistance of the MTJ is high when the magnetization directions of the magnetic reference and free layers are substantially anti-parallel or oriented in opposite directions. The stored logic in the magnetic memory element can be switched by changing the magnetization direction of the magnetic free layer between parallel and anti-parallel with respect to the magnetization direction of the reference layer. Therefore, the two stable resistance states enable the MTJ to serve as a non-volatile memory element.
The fast switching speed and low power consumption of MRAM make it an ideal replacement for DRAM. FIG. 1 illustrates a circuit diagram for a conventional DRAM device including a sensing circuitry. The DRAM device 50 includes a first array of memory cells 52 and a second array of memory cells 54 connected to a first and a second sense amplifier 56 and 58. The first and second arrays of memory cells 52 and 54 include a plurality of memory cells 60A-60L, each of which includes an access transistor 62 coupled to a storage capacitor 64 that acts as a memory element for storing a data bit. A plurality of parallel word lines 66A-66F extend along a row direction. Each of the word lines 66A-66F connects to gates of the access transistors 62 of a respective row of the memory cells 60A-60L. A plurality of parallel bit lines 68A-68D extend along a column direction. Each of the bit lines 68A-68D connects to drains of the access transistors 62 of a respective column of the memory cells 60A-60L. Each of the first and second sense amplifiers 56 and 58 is connected to one of the bit lines 68A-68B from the first array of memory cells 52 and one of the bit lines 68C-68D from the second array of memory cells 54.
In a sensing operation for reading a data bit from one of the memory cells 60A-60F, say the memory cell 60C connected to the bit line 68A and the word line 66B, all bit lines 68A-68D are first precharged to an intermediate voltage that is between a minimum voltage (e.g., 0 V) and and a maximum voltage (e.g., Vdd), which correspond to the voltages of the storage capacitor 64 in fully discharged and charged states, respectively. A voltage is then applied to the word line 66B to turn on the access transistors of all memory cells 60C-60D coupled thereto, thereby allowing the precharged bit lines 68A and 68B to electrically connect to the storage capacitors 64 of the memory cells 60C and 60D, respectively. Depending on the charge state of the storage capacitors 64 of the memory cells 60C and 60D, the voltages of the bit lines 68A and 68B may increase or decrease with respect to the initial precharged voltage. Using the sense amplifier 56, which consists essentially of a latch made of a pair of cross-connected inverters, the voltage of the bit line 68A connected to the sense amplifier 56 is compared with the precharged voltage of the bit line 68C that serves as the reference to determine the charge state of the storage capacitor 64 of the memory cell 60C. Owing to the positive feedback effect of the cross-connected inverters, the sense amplifier 56 amplifies the voltage difference between the two bit lines 68A and 68C until one of the two bit lines 68A and 68C is at the lowest voltage (e.g. 0 V) and the other one is at the highest voltage (e.g. Vdd), thereby latching the output of the sense amplifier 56 or the data bit corresponding to the memory cell 60C. Likewise, using the sense amplifier 58, the voltage of the bit line 68B is compared with the precharged voltage of the bit line 68D to determine the charge state of the storage capacitor 64 of the memory cell 60D. In the sensing operation described above, all memory cells 60C-60D connected to the selected word line 66B are sensed simultaneously, and the sense amplifier outputs are latched. A column address select then selects the desired latched bit corresponding to the memory cell 60C stored in the sense amplifier 56 for connection to the input/output (I/O) data bus.
Unlike DRAM that uses the relatively simple sense amplifier circuitry illustrated in FIG. 1, MRAM may require more complicated sense amplifier circuitry with significantly larger footprint to emulate DRAM, thereby adversely increasing the overhead for the memory device. For the foregoing reason, there is a need for a MRAM device that can emulate DRAM and that can be inexpensively manufactured.